1. Field
Example embodiments relate to a semiconductor device and a method of manufacturing the same. Other example embodiments relate to a non-volatile semiconductor flash memory device and a method of manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices are generally categorized as volatile memory devices, which lose data over time (e.g., a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device), or non-volatile memory devices, which continuously keep stored data over time (e.g., an electrically erasable programmable read only memory (EEPROM) device capable of inputting/outputting data or a flash memory device advanced from the EEPROM device). The non-volatile memory device generally used in various electronic apparatuses is the flash memory device. The flash memory device may electrically control inputting and outputting of data utilizing Fowler-Nordheim (F-N) tunneling mechanism or channel hot electron injection mechanism.
The flash memory devices may be classified according to structure as a NAND type flash memory device and a NOR type flash memory device. The NAND type flash memory device may include N numbers of unit cell transistors. The cell transistors may be electrically connected to one another in serial to form unit strings of the NAND type flash memory device. The unit strings of the NAND type flash memory device may be electrically connected to a bit line and a ground line in parallel. The NOR type flash memory device may include a plurality of cell transistors. Each of the cell transistors in the NOR type flash memory device may be electrically connected to a bit line and a ground line sequentially (or in parallel). The NOR type flash memory device may have a faster response speed. The NAND type flash memory device may have a higher integration degree.
A programming operation and an erasing operation of the NAND type flash memory device may be performed in a relatively short time. The programming and the erasing operations may be performed with low voltages. As such, a unit cell of the NAND type flash memory device may have a higher coupling ratio.
To increase the coupling ratio of the unit cell, a high capacitance may be established (or ensured) between a floating gate and a control gate. A low capacitance may be necessary between the floating gate and a substrate.
A dielectric layer interposed between the floating gate and the control gate may have a multi-layer structure that includes a lower silicon oxide film, a silicon nitride film and an upper silicon oxide film. The dielectric layer may be formed on a lateral portion of the floating gate to increase an effective area of the unit cell. Hence, the capacitance between the floating gate and the control gate may increase due to the dielectric layer.
To form the dielectric layer on the lateral portion of the floating gate, a desired distance may be provided between adjacent floating gates. When the distance between adjacent floating gates increases, a size of the unit cell may increase, deteriorating the integration degree of the nonvolatile memory device. When the distance between adjacent floating gates decreases, voids may be generated (or formed) in the control gate formed between adjacent floating gates. That is, the control gate formed between adjacent floating gates may have defects.
In order to increase the integration degree of the memory device, a line width of the floating gate may be decreased and/or a height of the floating gate may be increased. Therefore, fabricating processes for the floating gate may be complicated. Failures relating to the floating gate may occur due to complicated processes used to form the floating gate.